1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a non-volatile semiconductor memory device erasing data in units of blocks.
2. Description of the Background Art
A flash memory, one type of the non-volatile semiconductor memory devices, erases data in units of blocks. Specifically, in the flash memory, a high voltage is applied between a word line and a well & source line of a memory cell to perform an erase operation.
In a memory mat of the flash memory, when a word line and a bit line, or a word line and a well & source line, are short-circuited, the resulting leakage current will lower the level of the high voltage applied between the word line and the well & source line of the memory cell at the time of erase operation, and thus, the flash memory suffers an erase failure. Since the flash memory erases data in units of blocks, the erase failure occurs in units of blocks as well.
To recover the erase failure in the flash memory, a spare block is required for replacement on a block basis. Mounting a spare block to the flash memory inevitably increases the chip area. Thus, it is important in a floor plan (circuit layout design) of the flash memory to make a peripheral circuit effectively shared by normal blocks to suppress the increase of the chip area.
The floor plan of the flash memory is also important to suppress the adverse effect of the power supply noise on the peripheral circuit due to a high voltage generating circuit characteristic to the flash memory. Moreover, the floor plan of the flash memory is important to decrease the aspect ratio (width-length ratio) of a logic circuit band that is laid out using an automatic layout and wiring tool. The decrease of the aspect ratio of the logic circuit band can improve the degree of integration of the flash memory.
When a spare block is mounted to the flash memory, a non-selecting process of a defective block caused by a leakage current becomes critical. In a wafer test (WT) of the flash memory, a voltage stress apply test is performed on all blocks at once. At this time, it is necessary to suppress a voltage drop in the defective block due to the leakage current. To this end, application of the voltage stress to the defective block should be suppressed.
A non-volatile semiconductor memory device (flash memory) described in Japanese Patent Laying-Open No. 2001-084800 automatically detects an address of failure that would cause a decrease of an output voltage of a boost circuit in the batch write/erase test mode. The address is stored in a storage circuit to prevent a high voltage stress from being applied thereto, to thereby implement a batch write/erase test on memory cells that is performed prior to use of a redundant circuit.
The above-described non-volatile semiconductor memory device, however, monitors a change of the potential driven from a drive voltage generating circuit to determine a defective block, taking no account of floor plan. This leads to an increase of the chip area, and direct monitoring of the leakage current in the defective block is impossible.